The present invention claims priority from Japanese Patent Applications No. 11-340696 filed Nov. 30, 1999, No. 2000-191818 filed Jun. 26, 2000 and No. 2000-332754 filed Oct. 31, 2000, the contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to the test of a semiconductor device using an electron beam. Particularly, the present invention is suitable for use in a contact hole test.
2. Description of Related Art
In the recent semiconductor device, the size of semiconductor device is reduced more and more and the number of layers thereof is increased more and more in order to improve the performance of the semiconductor device. Therefore, the size of a structure to be formed by etching is in the order of 0.1 micron, so that it is particularly difficult to stably form fine contact-holes or via-holes. The contact-hole or via-hole is a hole formed in an insulating layer for electrically connecting a wiring formed on the insulating layer to a wiring underlying the insulating layer.
Since the size of such hole is reduced proportionally to the reduction of the size of semiconductor device and the operating clock frequency of semiconductor is increased, it is not enough for the contact-hole to merely provide an electric connection. That is, the transmission speed of electric signal through the contact-hole becomes a problem. For example, since a resistance value of one contact-hole is as large as 10 Kxcexa9 and a capacitance value between adjacent wiring is in the order of 0.01 pF or more, the time constant of the contact-hole becomes large enough to affect the rising speed of the clock with which the semiconductor device operates. If the time constant varies, the operating speed of a logic circuit varies. Therefore, it is necessary to wait until a decision is settled down. When the waiting time is long, there is a problem that a computation speed can not be improved even when the operating speed of elements constituting the logic circuit is improved.
In order to improve the operating speed of a whole semiconductor device, it is necessary to reduce the waiting time to as small value as possible by keeping an amount of delay of a rising edge of a clock signal, which is caused by the contact-hole, at a constant value or less. In order to realize such reduction of waiting time, it is necessary to manage the etching process for forming the contact-hole such that the diameter of the contact-hole becomes as designed. Further, if the diameter of the contact-hole is too large, it may contact with an adjacent element, causing unnecessary electric connection thereto to be formed. This is referred to as xe2x80x9cleakagexe2x80x9d and is one of defects of the semiconductor device. Therefore, it is necessary, in order to decide a contact-hole acceptable or not, to decide whether or not the diameter of the contact-hole is within a certain range with respect to a reference value.
In order to perform such decision, it has been usual that a bottom diameter of a contact-hole is measured by destroying a sample. As a first prior art method in such destructive measurement, there is a cross sectional SEM (Scanning Electron Microscope) measurement. In such method, a wafer is cut by using a glass cutter or FIB (Focused Ion Beam), etc., such that a cross section is taken exactly along a line passing through a center of the contact-hole. Then, the wafer is put on a sample table such that the cut plane becomes in parallel to the sample table and the cross section thereof is observed by a SEM to measure a longest distance of a bottom of the contact-hole on an image thereof Since the shape of the contact-hole is not always true circular, it is usual to measure distances in some directions and decide an average distance as the diameter of the bottom of the contact-hole. In order to measure an exact absolute diameter of the bottom, it is usual to compare a standard distance on the image with the displayed distance of the bottom of the contact-hole by observing the standard distance and the distance of the sample, simultaneously.
In a second prior art method, an oxide film formed on a surface of a sample, in which a contact-hole is formed, is removed by etching or CMP (Chemical/Mechanical Polishing), etc. On the surface of the sample from which the oxide film is removed, there is a mark left, which is produced when the contact-hole is etched and reflects a shape of a bottom of the contact-hole. The sample is put on a sample table such that the etching mark becomes in parallel to the sample table and the etching mark is observed by a SEM to measure a distance of the etching mark. The second method is featured by the fact that the preciseness of the measurement is high compared with the first method since the preciseness does not depend on the preciseness of cutting the sample.
However, these prior art methods are destructive methods as mentioned previously and there is a problem that it is impossible to directly measure a product. Further, since the SEM measurement is performed manually, there is another problem that the measurement takes long time and it is impossible to process a number of samples at high speed. Therefore, there is a further problem that the number of measuring points for each wafer is very small and the reliability of measurement is degraded.
As means for solving these problem, JP 10-281746A filed by the assignee of the present invention discloses a technique in which a current produced by electron beam passed through a contact-hole and reached a substrate is detected, from which a position and a size of a bottom portion of the contact-hole are detected. JP 4-62857A discloses a technique in which a sample is irradiated with not electron beam but ion beam to observe a secondary electron image by measuring a substrate current produced by the irradiation of ion beam. In JP 2000-174077A published on Jun. 23, 2000, a technique for testing a number of contact-holes within a short time is disclosed, in which a semiconductor wafer is sectioned to a plurality of regions and a ratio of normal contact-hole in each region is tested. Further, JP 2000-174077A discloses a technique for displaying the measured ratios correspondingly to the respective regions.
An object of the present invention is to provide a semiconductor tester and a semiconductor test method, which is capable of testing a semiconductor device at high speed without destroying the semiconductor device, by improving the technique for detecting a substrate current produced by irradiating the semiconductor device with electron beam.
The present invention is featured by that, by utilizing the principle of measurement of characteristics of a semiconductor device including a structure thereof on the basis of an amount of current produced in a sample by irradiation of low energy electron beam, characteristics of an arbitrary region of the sample is measured at high speed without destroying the sample by setting a measurement mode according to a measuring object.
That is, according to a first aspect of the present invention, a semiconductor device is provided, which comprises means for sequentially irradiating a plurality of measuring positions on a sample with electron beams having identical cross sectional shapes, means for measuring a current produced in the sample when individual measuring positions are irradiated with electron beams, and display means for displaying the measured currents or physical amounts derived from the measured currents on a two-dimensional plane as not mere numerical values but a function of measuring position and measuring region. The measuring means preferably measures a total amount of currents produced when the individual measuring positions of the sample are irradiated with an electron beam.
The present invention can be utilized in testing various semiconductor devices and, particularly, in testing contact-holes of various semiconductor devices. In the latter case, the irradiating means preferably irradiates positions of a semiconductor wafer having a single contact-hole or a plurality of contact-holes, which are arranged along an arbitrary axis crossing the wafer with a predetermined interval, preferably, with an interval having a predetermined period, with electron beam.
A stepper exposing device may be used as the irradiating means. In such case, it is preferable to irradiate positions of the wafer, which are separated with a predetermined interval in a shot region that is a range exposed in one stepper exposure, with electron beam. More preferably, positions, which are arranged with a predetermined interval along an arbitrary axis passing through a scribe region determining a region of one semiconductor device, are irradiated with electron beam.
The display means preferably includes means for evaluating an amount of current in each of the measuring positions according to a quality determination algorithm determined every semiconductor device and displaying specific symbols on a two-dimensional plane simulating a wafer shape correspondingly to normal or defective positions. It may further include means for displaying a specific symbol corresponding to a defective mode according to the defective mode determined every semiconductor device.
Further, the display means may include means for evaluating an amount of current in each of the measuring positions according to a quality determination algorithm determined every semiconductor device and displaying values or substantial values of diameters of contact-holes on a two-dimensional plane simulating a wafer shape correspondingly to the measuring positions. In such case, it may be possible to display a symbol indicating a range of the contact-hole diameter, to display values of the contact-hole diameter as contours, to display colors indicating ranges of values of the contact-hole diameters or to display magnitudes of measured currents corresponding to spacial frequencies on a two-dimensional plane by calculating the spacial frequencies of the measured current amounts. Alternatively, it may be possible to display a ratio of contact-hole diameter every wafer as a function of the contact-hole diameter, to display a ratio of contact-hole diameter every shot of the stepper exposure as a function of the contact-hole diameter, to display a ratio of contact-hole diameter every chip on a wafer as a function of the contact-hole or to display a statistical amount of such as maximum diameter, minimum diameter, average diameter, standard deviation and/or deviation from a standard diameter of the contact-hole every wafer.
The present invention can be utilized in a test of an electrically conductive substrate, in which holes are formed by using a photo resist formed on the substrate as a mask. In such case, the present invention preferably includes means for extracting contact-holes having the same designed size from a layout information of a mask used in exposure and assigning contact-holes to be tested every chip within a range, which is exposed simultaneously when it is exposed during the exposure of the photo resist.
The present invention can be utilized in a test of an element having contact-holes whose depths are different. In such case, the present invention preferably includes means for classifying the contact-holes every depth thereof on the basis of design data of these contact holes and controlling the irradiating means such that the contact-holes in each group are irradiated with electron beam. In such case, the display means preferably include means for simultaneously displaying a design sheet corresponding to the depths of the respective contact-holes and a secondary electron image representing a surface of the element.
It is possible to measure a plurality of individual measuring positions not one by one but at once. That is, the present invention may include means for classifying a plurality of measuring positions on the sample to a plurality of regions and controlling the irradiating means such that every region is irradiated with electron beam and the display means may include average value display means for displaying an amount of current measured in every region as an average amount of currents obtained in a plurality of measuring positions contained in the region.
Further, the irradiating means is capable of switching an operation mode between a first mode in which the plurality of measuring positions classified to a plurality of regions and every region is irradiated with electron beam and a second mode in which individual measuring positions are irradiated with electron beam and may include control means for setting the irradiating means to the first mode, classifying the amounts of currents measured by the measuring means according to the magnitudes thereof, selecting some of the regions according to a predetermined reference, setting the irradiating means to the second mode for the selected regions and repeating the measurement.
The present invention may include memory means storing measuring position patterns suitable for items to be tested, means for reading one of the measuring position pattern from the memory means corresponding to a test item selected by an operator, converting the measuring positions into coordinates for which the test is performed practically by extending the measuring pattern suitably for the size of an object to be measured and means for controlling the irradiating means such that the measuring positions assigned are irradiated with electron beam in an assigned sequence thereof on the basis of the practical coordinates obtained by the converting means.
The present invention can be utilized to determine process conditions for a mass-production of semiconductor device. In order to realize the mass-production, a plurality of test samples, which are formed by using mutually different process conditions and contain a plurality of regions in which test objects are formed in different densities, are used as the sample and the semiconductor device tester preferably includes means for comparing the amounts of currents measured by the measuring means when the plurality of the regions are irradiated with electron beam between process conditions, memory means for storing a result of comparison from the comparing means with using the process conditions used for the test samples as parameters and means for selecting an optimal process condition from the result of comparison related to the plurality of the test sample stored in the memory means.
In the latter case, the plurality of the regions may include first regions in which the objects to be tested are formed in high density and second regions in which the objects to be tested are formed discretely. In a case where the objects to be tested are contact-holes, the comparing means preferably includes means for comparing an amount of current flowing in one contact-hole within the first region with an amount of current flowing in one discrete contact-hole within the second region. Alternatively, the comparing means may include means for comparing an amount of current flowing in one contact-hole within the first region, which is obtained by normalizing currents flowing in a plurality of contact-holes within the first region with the number of the contact-holes with an amount of current flowing in one discrete contact-hole within the second region.
Similar test can be performed for wiring patterns. Further, the plurality of the regions may include a first region in which objects to be tested are formed in relatively high density, a second region in which objects to be tested in relatively low density and a third region in which discrete objects are formed.
The present invention can be utilized in a process test in a mass-production. In such case, the semiconductor device tester of the present invention preferably includes means for specifying a plurality of regions of the sample in which objects to be tested in different densities, means for comparing currents measured by the measuring means when the plurality of the regions are irradiated with electron beam, respectively, and means for alarming a fabrication step performed for the sample as abnormal when the result of comparison from the comparing means does not satisfy a predetermined condition.
The present invention can be executed by using not only an apparatus dedicated thereto but also an apparatus such as an electron beam exposing apparatus capable of irradiating specific region with electron beam or by a data processing using a general information processor.
That is, according to a second aspect of the present invention, a semiconductor device testing method is provided, which is featured by comprising a first step of measuring currents flowing in a sample by irradiating a plurality of measuring positions on the sample with electron beams sequentially such that the electron beams have identical cross sectional areas and storing the respective measuring positions and the measured currents and a second step of reading the currents and the measuring positions and displaying the currents or physical amount derived from the currents on a two dimensional plane as a function of the measuring positions.